1. Field of the Invention
The present invention relates to a data processing system and data processing method capable of halting the supply of a clock signal to individual blocks immediately when a clock supply stop instruction is executed.
2. Description of Related Art
FIG. 17 is a block diagram showing a configuration of a conventional data processing system disclosed in Japanese patent application laid-open No. 5-197627/1993, for example. In FIG. 17, the reference numeral 1 designates a CPU for carrying out pipeline processing that decodes the next instruction while executing a current instruction; 2 designates a memory for storing programs to be executed by the CPU 1; 3 and 4 each designate peripheral equipment for executing predetermined operations; and 5 designates a clock power manager for controlling supply of the clock signal to individual blocks such as CPU 1, memory 2 and peripheral equipment 3 and 4.
FIG. 18 is a block diagram showing a configuration of the clock power manager 5, in which the reference numeral 6 designates an identity decision block that outputs, if the address placed on the address bus by the CPU 1 agrees with the self-address of the identity decision block 6 when the CPU 1 outputs a write enable signal, an operation enable command for enabling writing of data placed on the data bus by the CPU 1. The reference numeral 7 designates a mode transition register that stores, in response to the operation enable command from the identity decision block 6, the data placed on the data bus by the CPU 1; 8 designates an identity decision block that outputs, in response to the operation enable command from the identity decision block 6, a clock stop signal if the data stored in the mode transition register 7 instructs to halt the clock supply; and 9 designates a clock halt block that suspends, in response to the clock stop signal from the identity decision block 8, the supply of the clock signal to respective blocks.
Next, the operation of the conventional data processing system will be described.
First, the CPU 1 carries out the pipeline processing that decodes subsequent instructions while executing the current instruction as illustrated in FIG. 19.
More specifically, assume that the operation of the CPU 1 involved in executing an instruction is partitioned into the following four phases, for example: an instruction fetch phase IF that fetches an instruction from a program in the memory 2; an instruction decode phase ID that decodes the instruction; an execute phase EX that performs in accordance with the instruction a predetermined operation by acquiring data from the memory or registers; and a write back phase WB that writes an execution result back to the memory 2 or the mode transition register 7. In that case, when the instruction 1 is in the write back phase WB, for example, the instruction 2 next to the instruction 1 is in the execute phase EX, and the instruction 3 next to the instruction 2 is in the instruction decode phase ID.
Now, the case will be described where the CPU 1 executes the clock stop instruction.
First, fetching the instruction from the program in the memory 2 in the instruction fetch phase IF, the CPU 1 decodes the instruction in the instruction decode phase ID, and recognizes that the instruction is the clock stop instruction.
Subsequently, the CPU 1 supplies, in the execute phase EX, the data bus with data instructing to halt the supply of the clock signal, the address bus with the address of the identity decision block 6, and the control signal line with a write enable signal.
In response to that, the identity decision block 6 decides, in the execute phase EX, whether or not the address on the address bus agrees with the self-address of the identity decision block 6, and outputs the operation enable command that allows writing of data if they agree.
Receiving the operation enable command from the identity decision block 6, the mode transition register 7 shifts, in the write back phase WB, into a data write enabled state, and writes the data placed on the data bus by the CPU 1. Note that when the clock stop instruction is in the write back phase WB, the next instruction is in the execute phase EX as shown in FIG. 20.
Thus, when the mode transition register 7 writes the data in response to the operation enable command supplied from the identity decision block 6, and if the data stored in the mode transition register 7 instructs to halt the supply of the clock signal, the identity decision block 8 outputs the clock stop signal. Receiving the clock stop signal from the identity decision block 8, the clock halt block 9 suspends the supply of the clock signal to the individual blocks, which causes these blocks such as the CPU 1, memory 2, peripheral equipment 3 and 4 to halt their operations.
With the foregoing arrangement, the conventional data processing system has a problem of having executed the instruction next to the clock stop instruction, when the CPU 1 executed the clock stop instruction. This is because although the supply of the clock signal to the blocks is suspended when the CPU 1 executes the clock stop instruction, the clock power manager 5 supplies the clock halt block 9 with the clock stop signal when the clock stop instruction shifts into the write back phase WB, in which case the next instruction has already shifted into the execute phase EX.
Incidentally, Japanese patent application laid-open No. 2-249199/1990 discloses a technique for comparing the address data to prevent erroneous writing of an involatile memory, and Japanese patent application laid-open No. 5-224966/1993 discloses a technique for preventing erroneous operation by writing "1" into a flag at a time when executing the stop operation. These techniques, however, do not consider the pipeline processing, and hence cannot prevent the instruction next to the clock stop instruction from being executed because the next instruction proceeds to the execute phase EX while the clock stop instruction is in the write back phase WB.